Solaris cc compiler on amd: PostgreSQL does not have native spinlock support on this platform
Hello,
I'm trying to compile postgresql and I got this message telling me
to inform you:
"../../../../src/include/storage/s_lock.h", line 806: #error: PostgreSQL
does not have native spinlock support on this platform. To continue the
compilation, rerun configure using --disable-spinlocks. However,
performance will be poor. Please report this to pgsql-bugs@postgresql.org.
This is the configure line i used:
MAKE=gmake CC=/opt/SUNWspro/bin/cc CFLAGS="-xtarget=opteron
-xarch=amd64" CXX=/opt/SUNWspro/bin/CC CXXFLAGS="-xtarget=opteron
-xarch=amd64" LDFLAGS="-xtarget=opteron -xarch=amd64" ./configure
--without-readline
If i try this configuration command instead:
MAKE=gmake CC=/opt/SUNWspro/bin/cc CFLAGS="-fast"
CXX=/opt/SUNWspro/bin/CC CXXFLAGS="-fast" LDFLAGS="-fast" ./configure
--without-readline
It compiles but then i get a 32 bit executable which is not what i want.
This is on a solaris 10 with amd processor using the sun forte 11 compilers.
Are there any fix for this?
Thanks.
Pierre Girard <pierre.girard@gerad.ca> writes:
It compiles but then i get a 32 bit executable which is not what i want.
This is on a solaris 10 with amd processor using the sun forte 11 compilers.
Are there any fix for this?
You'd need to do something about adapting src/backend/port/tas/solaris_i386.s
to amd64, and then change the part of s_lock.h that mentions Solaris/386
to also accept x86_64 not just __i386. Also see src/template/solaris
which controls configure's determination of which tas file is needed.
It's possible that the assembly code would work as-is on amd, in which
case you'd just need a one-liner change in s_lock.h and maybe some
adjustment of the template file.
Please send a patch if you fix this.
regards, tom lane
Tom Lane wrote:
You'd need to do something about adapting src/backend/port/tas/solaris_i386.s
It's possible that the assembly code would work as-is on amd, in which
case you'd just need a one-liner change in s_lock.h and maybe some
adjustment of the template file.
It doesn't compile with the options to create amd code.
cc -Xa -xtarget=opteron -xarch=amd64 -c solaris_i386.s
Assembler: tas.s
"solaris_i386.s", line 12 : Illegal mnemonic
"solaris_i386.s", line 14 : Illegal mnemonic
"solaris_i386.s", line 15 : Syntax error
"solaris_i386.s", line 17 : Syntax error
"solaris_i386.s", line 26 : Illegal mnemonic
"solaris_i386.s", line 28 : Illegal mnemonic
cc: assembler failed for solaris_i386.s
The same file compiles without those options:
cc -Xa -c solaris_i386.s
Please send a patch if you fix this.
Unfortunately i won't be able to help unless you have some code for me
to try out.
Pierre Girard wrote:
Tom Lane wrote:
You'd need to do something about adapting src/backend/port/tas/solaris_i386.s
It's possible that the assembly code would work as-is on amd, in which
case you'd just need a one-liner change in s_lock.h and maybe some
adjustment of the template file.It doesn't compile with the options to create amd code.
cc -Xa -xtarget=opteron -xarch=amd64 -c solaris_i386.s
Assembler: tas.s
"solaris_i386.s", line 12 : Illegal mnemonic
"solaris_i386.s", line 14 : Illegal mnemonic
"solaris_i386.s", line 15 : Syntax error
"solaris_i386.s", line 17 : Syntax error
"solaris_i386.s", line 26 : Illegal mnemonic
"solaris_i386.s", line 28 : Illegal mnemonic
cc: assembler failed for solaris_i386.sThe same file compiles without those options:
cc -Xa -c solaris_i386.s
Interesting. Seems you have a setup that uses its own assembly source
file in port/tas/solaris_i386.s, rather than using inline C ASM. There
are files for both Sparc and i386 there, and are both used only for the
Sun compiler. Does the Sun compiler not support ASM inlining?
Looking at the error line, it is:
pushl %ebp /save prev base pointer
and then:
pushl %ebx /save prev bx
Looks like it is all documented here:
http://www.x86-64.org/documentation/assembly
Specifically:
Exceptions from this rule are instructions manipulating the stack (push,
pop, call, ret, enter and leave) which are implicitly 64-bit and their
32-bit counterparts are not available anymore, yet their 16-bit
counterparts are. So:
pushl %eax # Illegal instruction
pushq %rax # 1 byte instruction encoded as pushl %eax in 32 bits
pushq %r10 # 2 byte instruction encoded as pushl preceeded by REX.
Looking before that, the 64-bit registers are now prefixed with 'r'
instead of 'e', so what I did was to convert all the long/l assembler
instructions to quad/64-bit/q, and rename the registers to use 64-bit
versions. I also modified the function alignment from 4 to 8, patch
attached. Please give it a try and report back any error lines.
Seems Sun might be interested in geting this working. We don't have an
official Sun contact yet for this project.
--
Bruce Momjian | http://candle.pha.pa.us
pgman@candle.pha.pa.us | (610) 359-1001
+ If your life is a hard drive, | 13 Roberts Road
+ Christ can be your backup. | Newtown Square, Pennsylvania 19073Attachments:
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Index: src/backend/port/tas/solaris_i386.s
===================================================================
RCS file: /cvsroot/pgsql/src/backend/port/tas/solaris_i386.s,v
retrieving revision 1.2
diff -c -c -r1.2 solaris_i386.s
*** src/backend/port/tas/solaris_i386.s 19 Jun 1998 02:55:09 -0000 1.2
--- src/backend/port/tas/solaris_i386.s 17 Dec 2005 20:57:07 -0000
***************
*** 9,33 ****
.globl tas
tas:
! pushl %ebp /save prev base pointer
! movl %esp,%ebp /new base pointer
! pushl %ebx /save prev bx
! movl 8(%ebp),%ebx /load bx with address of lock
! movl $255,%eax /put something in ax
! xchgb %al,(%ebx) /swap lock value with "0"
cmpb $0,%al /did we get the lock?
jne .Locked
! subl %eax,%eax /yes, we got it -- return 0
jmp .Finish
! .align 4
.Locked:
! movl $1,%eax /no, we didn't get it - return 1
.Finish:
! popl %ebx /restore prev bx
! movl %ebp,%esp /restore stack state
! popl %ebp
ret /return
! .align 4
.type tas,@function
.size tas,.-tas
--- 9,33 ----
.globl tas
tas:
! pushq %rbp /save prev base pointer
! movq %rsp,%rbp /new base pointer
! pushq %rbx /save prev bx
! movq 8(%rbp),%rbx /load bx with address of lock
! movq $255,%rax /put something in ax
! xchgb %al,(%rbx) /swap lock value with "0"
cmpb $0,%al /did we get the lock?
jne .Locked
! subq %rax,%rax /yes, we got it -- return 0
jmp .Finish
! .align 8
.Locked:
! movq $1,%rax /no, we didn't get it - return 1
.Finish:
! popq %rbx /restore prev bx
! movq %rbp,%rsp /restore stack state
! popq %rbp
ret /return
! .align 8
.type tas,@function
.size tas,.-tas
Bruce Momjian <pgman@candle.pha.pa.us> writes:
Looking before that, the 64-bit registers are now prefixed with 'r'
instead of 'e', so what I did was to convert all the long/l assembler
instructions to quad/64-bit/q, and rename the registers to use 64-bit
versions. I also modified the function alignment from 4 to 8, patch
attached. Please give it a try and report back any error lines.
Surely that breaks it for the i386 case --- don't we need a separate
solaris_x86_64.s source file?
regards, tom lane
Tom Lane wrote:
Bruce Momjian <pgman@candle.pha.pa.us> writes:
Looking before that, the 64-bit registers are now prefixed with 'r'
instead of 'e', so what I did was to convert all the long/l assembler
instructions to quad/64-bit/q, and rename the registers to use 64-bit
versions. I also modified the function alignment from 4 to 8, patch
attached. Please give it a try and report back any error lines.Surely that breaks it for the i386 case --- don't we need a separate
solaris_x86_64.s source file?
Yes, it is only for him to test. But his email bounced back so it is
possible he isn't going to be back. :-(
--
Bruce Momjian | http://candle.pha.pa.us
pgman@candle.pha.pa.us | (610) 359-1001
+ If your life is a hard drive, | 13 Roberts Road
+ Christ can be your backup. | Newtown Square, Pennsylvania 19073
On Sat, Dec 17, 2005 at 04:59:45PM -0500, Bruce Momjian wrote:
Tom Lane wrote:
Bruce Momjian <pgman@candle.pha.pa.us> writes:
Looking before that, the 64-bit registers are now prefixed with 'r'
instead of 'e', so what I did was to convert all the long/l assembler
instructions to quad/64-bit/q, and rename the registers to use 64-bit
versions. I also modified the function alignment from 4 to 8, patch
attached. Please give it a try and report back any error lines.Surely that breaks it for the i386 case --- don't we need a separate
solaris_x86_64.s source file?Yes, it is only for him to test. But his email bounced back so it is
possible he isn't going to be back. :-(
Sorry, I don't remember the history of this thread, but I do have access
to solaris on an opteron if something needs to be tested.
--
Jim C. Nasby, Sr. Engineering Consultant jnasby@pervasive.com
Pervasive Software http://pervasive.com work: 512-231-6117
vcard: http://jim.nasby.net/pervasive.vcf cell: 512-569-9461
Jim C. Nasby wrote:
On Sat, Dec 17, 2005 at 04:59:45PM -0500, Bruce Momjian wrote:
Tom Lane wrote:
Bruce Momjian <pgman@candle.pha.pa.us> writes:
Looking before that, the 64-bit registers are now prefixed with 'r'
instead of 'e', so what I did was to convert all the long/l assembler
instructions to quad/64-bit/q, and rename the registers to use 64-bit
versions. I also modified the function alignment from 4 to 8, patch
attached. Please give it a try and report back any error lines.Surely that breaks it for the i386 case --- don't we need a separate
solaris_x86_64.s source file?Yes, it is only for him to test. But his email bounced back so it is
possible he isn't going to be back. :-(Sorry, I don't remember the history of this thread, but I do have access
to solaris on an opteron if something needs to be tested.
If you set up Solaris in 64-bit mode, and are using the Sun compiler,
please test the patch I posted and let me know if it compiles:
http://archives.postgresql.org/pgsql-patches/2005-12/msg00275.php
--
Bruce Momjian | http://candle.pha.pa.us
pgman@candle.pha.pa.us | (610) 359-1001
+ If your life is a hard drive, | 13 Roberts Road
+ Christ can be your backup. | Newtown Square, Pennsylvania 19073